TF112 - 7 Port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Product Type: System Test
Current Status: Final

Product Overview
The TF112 combines a 7 port IEEE1149.1 (JTAG) multiplexer with addressable multidrop capability. As a multiplexer, 7 local ports allow partitioning of scan chains to simplify and accelerate programming and test and debug sequences. Optional daughter cards or ICs are easily handled with dedicated scan chains. Local chains can be selected individually or in combination as required.
Addressable multi-drop capability allows operation on a backplane with other TF112s or similar addressable devices. 8 address pins are used to set the unique device address. Ad- dressing the device is accomplished by loading the instruction register with a value matching the address pins. The backplane port and one of the local ports are bi-directional and may be set as master or slave. This feature enables multi- master operation.
All major ATPG vendors support this function and both addressing and selection of local ports is handled automatically by the vector generation software.

Features

• ATPG support from all major vendors
• Fully pin and function compatible with NSC SCANSTA112
• Muxes 7 local JTAG ports from 1 source
• Supports multidrop addressing
• Backplane Port and LSP0 can act as slave/master for multi-master operation
• Supports live insertion
• Transparent Mode for simplified FPGA/CPLD programming
• Pass-thru bits can be driven by pins or internal registers to assist Flash Programming